The present invention relates to a test pattern generator, and more particularly to a test pattern generator suitable for testing a complex device having a memory unit and a logical unit.
Various complex devices such as LSI devices having both memory units and logical units, multichips and the like have been developed with the help of high integration and high performance of recent LSI devices.
Generally, a test of specific functions of complex devices is carried out with a memory tester for a memory unit and with a logic tester for a logic unit. Otherwise, if a memory unit is tested with a logic tester, test patterns for a memory unit are stored beforehand in a pattern memory of the logic tester.
A test pattern generator of this type is known, for example, as disclosed in JP-A-55-52967. With this test pattern generator, patterns of two types are selectively generated by subjecting a support memory under the control of microprograms which also control a pattern generator used for producing regular address sequences for a memory unit test, the support memory being used for producing random address sequences for a logic unit test.
With this test pattern generator, however, it is difficult to obtain a perfect test result, such as in a consecutive operation/function test of a multiport section of a complex device as shown in FIG. 6 between its memory unit 20 and its logic unit, in a consecutive switching and reading test of multimemory cells, or in other tests. Further, each of a plurality of test patterns must be changed frequently for each pin or for each block of plural pins, so that it is impossible to efficiently perform pin assignment to each test pattern.
Another prior art technology changing test patterns for each pin of an LSI device in real time is disclosed in "Model GR18, General Purposes Complex VLSI Test System, Standard Product Description and Specification" by General Semiconductor Test Inc. According to this technology, the problem associated with pin assignment to each test pattern can be solved. However, in this publication, there is no disclosure of a particular construction of the test pattern selector for changing sequential pattern data for each pin in real time. Moreover, the pin control table used in controlling the test pattern selector is a memory array of 4k.times.4 bits. Since the pin control table is required to produce control signals for changing the test pattern data in real time, the amount of data stored in the memory becomes very large. Further, if the data is different for each pin, it is necessary to prepare a pin control table for each pin, thus resulting in a large system of pin control tables. Apart from the above, there is a tendency nowadays of increasing the number of test pins to reduce test time. Thus, the scale of pin control tables becomes very large.